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cmos, 330 mhz triple 10-bit high speed video dac adv7123 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features 330 msps throughput rate triple 10-bit digital-to-analog converters (dacs) sfdr ?70 db at f clk = 50 mhz; f out = 1 mhz ?53 db at f clk = 140 mhz; f out = 40 mhz rs-343a-/rs-170-compatible output complementary outputs dac output current range: 2.0 ma to 26.5 ma ttl-compatible inputs internal reference (1.235 v) single-supply 5 v/3.3 v operation 48-lead lqfp package low power dissipation (30 mw minimum @ 3 v) low power standby mode (6 mw typical @ 3 v) industrial temperature range (?40c to +85c) pb-free (lead-free) package applications digital video systems (1600 1200 @ 100 hz) high resolution color graphics digital radio modulation image processing instrumentation video signal reconstruction functional block diagram 10 10 10 10 10 10 data register dac dac blank sync r9 to r0 g9 to g0 b9 to b0 psave clock dac adv7123 data register data register blank and sync logic power-down mode voltage reference circuit ior ior iog iog iob v ref r set v aa comp gnd iob 00215-001 figure 1. general description the adv7123 (adv?) is a triple high speed, digital-to-analog converter on a single monolithic chip. it consists of three high speed, 10-bit, video dacs with complementary outputs, a standard ttl input interface, and a high impedance, analog output current source. the adv7123 has three separate 10-bit-wide input ports. a single 5 v/3.3 v power supply and clock are all that are required to make the part functional. the adv7123 has additional video control signals, composite sync and blank . the adv7123 also has a power save mode. the adv7123 is fabricated in a 5 v cmos process. its monolithic cmos construction ensures greater functionality with lower power dissipation. the adv7123 is available in a 48-lead lqfp package. product highlights 1. 330 msps throughput. 2. guaranteed monotonic to 10 bits. 3. compatible with a wide variety of high resolution color graphics systems, including rs-343a and rs-170. adv is a registered trademar k of analog devices, inc.
adv7123 rev. d | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 5 v specifications ......................................................................... 3 3.3 v specifications ...................................................................... 4 5 v dynamic specifications ........................................................ 5 3.3 v dynamic specifications ..................................................... 6 5 v timing specifications ........................................................... 7 3.3 v timing specifications ........................................................ 8 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 5 v typical performance characteristics ................................ 12 3 v typical performance characteristics ................................ 14 terminology .................................................................................... 16 circuit description and operation .............................................. 17 digital inputs .............................................................................. 17 clock input .................................................................................. 17 video synchronization and control ........................................ 18 reference input ........................................................................... 18 dacs ............................................................................................ 18 analog outputs .......................................................................... 18 gray scale operation ................................................................. 19 video output buffers ................................................................. 19 pcb layout considerations ...................................................... 19 digital signal interconnect ....................................................... 19 analog signal interconnect....................................................... 20 outline dimensions ....................................................................... 21 ordering guide .......................................................................... 21 revision history 7/10rev. c to rev. d changes to figure 2 .......................................................................... 9 changes to figure 22 and figure 23 ............................................. 17 changes to table 9 .......................................................................... 18 3/09rev. b to rev. c updated format .................................................................. universal changes to features section............................................................ 1 changes to table 5 ............................................................................ 7 changes to table 6 ............................................................................ 8 changes to table 8 .......................................................................... 10 changed f clock to f clk ..................................................................... 12 changes to figure 6, figure 7, and figure 8................................ 12 changes to figure 13 and figure 17 ............................................. 14 deleted ground planes section, power planes section, and supply decoupling section ........................................................... 15 changes to figure 23 ...................................................................... 17 changes to table 9, analog outputs section, figure 24, and figure 25 .......................................................................................... 18 changes to video output buffers section and pcb layout considerations section .................................................................. 19 changes to analog signal interconnect section and figure 28 .......................................................................................... 20 updated outline dimensions ....................................................... 21 changes to ordering guide .......................................................... 21 10/02rev. a to rev. b change in title ................................................................................... 1 change to feature .............................................................................. 1 change to product highlights ......................................................... 1 change specifications ....................................................................... 3 change to pin function descriptions ......................................... 10 change to reference input section .............................................. 18 change to figure 28 ....................................................................... 22 updated outline dimensions ....................................................... 23 change to ordering guide ............................................................ 23
adv7123 rev. d | page 3 of 24 specifications 5 v specifications v aa = 5 v 5%, v ref = 1.235 v, r set = 560 , c l = 10 pf. all specifications t min to t max , 1 unless otherwise noted, t j max = 110c. table 1. parameter min typ max unit test conditions 1 static performance resolution (each dac) 10 bits integral nonlinearity (bsl) ?1 0.4 +1 lsb differential nonlinearity ?1 0.25 +1 lsb guaranteed monotonic digital and control inputs input high voltage, v ih 2 v input low voltage, v il 0.8 v input current, i in ?1 +1 a v in = 0.0 v or v dd psave pull-up current 20 a input capacitance, c in 10 pf analog outputs output current 2.0 26.5 ma green dac, sync = high 2.0 18.5 ma rgb dac, sync = low dac-to-dac matching 1.0 5 % output compliance range, v oc 0 1.4 v output impedance, r out 100 k output capacitance, c out 10 pf i out = 0 ma offset error ?0.025 +0.025 % fsr tested with dac output = 0 v gain error 2 ?5.0 +5.0 % fsr fsr = 17.62 ma voltage reference, external and internal reference range, v ref 1.12 1.235 1.35 v power dissipation digital supply current 3 3.4 9 ma f clk = 50 mhz 10.5 15 ma f clk = 140 mhz 18 25 ma f clk = 240 mhz analog supply current 67 72 ma r set = 560 8 ma r set = 4933 standby supply current 4 2.1 5.0 ma psave = low, digital, and control inputs at v dd power supply rejection ratio 0.1 0.5 %/% 1 temperature range t min to t max : ?40c to +85c at 50 mh z and 140 mhz, 0c to 70 c at 240 mhz and 330 mhz. 2 gain error = {(measured (fsc)/ideal (fsc) ? 1) 100}, where ideal = v ref /r set k (0x3ffh) and k = 7.9896. 3 digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 v and v dd . 4 these maximum/minimum specifications are guaranteed by characterization to be over the 4.75 v to 5.25 v range.
adv7123 rev. d | page 4 of 24 3.3 v specifications v aa = 3.0 v to 3.6 v, v ref = 1.235 v, r set = 560 , c l = 10 pf. all specifications t min to t max , 1 unless otherwise noted, t j max = 110c. table 2. parameter 2 min typ max unit test conditions 1 static performance resolution (each dac) 10 bits r set = 680 integral nonlinearity (bsl) ?1 +0.5 +1 lsb r set = 680 differential nonlinearity ?1 +0.25 +1 lsb r set = 680 digital and control inputs input high voltage, v ih 2.0 v input low voltage, v il 0.8 v input current, i in ?1 +1 a v in = 0.0 v or v dd psave pull-up current 20 a input capacitance, c in 10 pf analog outputs output current 2.0 26.5 ma green dac, sync = high 2.0 18.5 ma rgb dac, sync = low dac-to-dac matching 1.0 % output compliance range, v oc 0 1.4 v output impedance, r out 70 k output capacitance, c out 10 pf offset error 0 0 % fsr tested with dac output = 0 v gain error 3 0 % fsr fsr = 17.62 ma voltage reference, external reference range, v ref 1.12 1.235 1.35 v voltage reference, internal voltage reference, v ref 1.235 v power dissipation digital supply current 4 2.2 5.0 ma f clk = 50 mhz 6.5 12.0 ma f clk = 140 mhz 11 15 ma f clk = 240 mhz 16 ma f clk = 330 mhz analog supply current 67 72 ma r set = 560 8 ma r set = 4933 standby supply current 2.1 5.0 ma psave = low, digital, and control inputs at v dd power supply rejection ratio 0.1 0.5 %/% 1 temperature range t min to t max : ?40c to +85c at 50 mh z and 140 mhz, 0c to 70 c at 240 mhz and 330 mhz. 2 these maximum/minimum specifications ar e guaranteed by characterization to be over the 3.0 v to 3.6 v range. 3 gain error = {(measured (fsc)/ideal (fsc) ? 1) 100}, where ideal = v ref /r set k (0x3ffh) and k = 7.9896. 4 digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 v and v dd .
adv7123 rev. d | page 5 of 24 5 v dynamic specifications v aa = 5 v 5%, 1 v ref = 1.235 v, r set = 560 , c l = 10 pf. all specifications are t a = 25c, unless otherwise noted, t j max = 110c. table 3. parameter 1 min typ max unit ac linearity spurious-free dynamic range to nyquist 2 single-ended output f clk = 50 mhz; f out = 1.00 mhz 67 dbc f clk = 50 mhz; f out = 2.51 mhz 67 dbc f clk = 50 mhz; f out = 5.04 mhz 63 dbc f clk = 50 mhz; f out = 20.2 mhz 55 dbc f clk = 100 mhz; f out = 2.51 mhz 62 dbc f clk = 100 mhz; f out = 5.04 mhz 60 dbc f clk = 100 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 40.4 mhz 48 dbc f clk = 140 mhz; f out = 2.51 mhz 57 dbc f clk = 140 mhz; f out = 5.04 mhz 58 dbc f clk = 140 mhz; f out = 20.2 mhz 52 dbc f clk = 140 mhz; f out = 40.4 mhz 41 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz 70 dbc f clk = 50 mhz; f out = 2.51 mhz 70 dbc f clk = 50 mhz; f out = 5.04 mhz 65 dbc f clk = 50 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 2.51 mhz 67 dbc f clk = 100 mhz; f out = 5.04 mhz 63 dbc f clk = 100 mhz; f out = 20.2 mhz 58 dbc f clk = 100 mhz; f out = 40.4 mhz 52 dbc f clk = 140 mhz; f out = 2.51 mhz 62 dbc f clk = 140 mhz; f out = 5.04 mhz 61 dbc f clk = 140 mhz; f out = 20.2 mhz 55 dbc f clk = 140 mhz; f out = 40.4 mhz 53 dbc spurious-free dynamic range within a window single-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 77 dbc f clk = 50 mhz; f out = 5.04 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.04 mhz; 4 mhz span 64 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 74 dbc f clk = 50 mhz; f out = 5.00 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.00 mhz; 4 mhz span 60 dbc total harmonic distortion f clk = 50 mhz; f out = 1.00 mhz t a = 25c 66 dbc t min to t max 65 dbc f clk = 50 mhz; f out = 2.00 mhz 64 dbc f clk = 100 mhz; f out = 2.00 mhz 63 dbc f clk = 140 mhz; f out = 2.00 mhz 55 dbc
adv7123 rev. d | page 6 of 24 parameter 1 min typ max unit dac performance glitch impulse 10 pv-sec dac-to-dac crosstalk 3 23 db data feedthrough 4 , 5 22 db clock feedthrough 4 , 5 33 db 1 these maximum/minimum specifications are guaranteed by characterization over the 4.75 v to 5.25 v range. 2 note that the adv7123 exhibits high performance when operating with an internal voltage reference, v ref . 3 dac-to-dac crosstalk is measured by holding one dac high wh ile the other two are making low-to-high and high-to-low transition s. 4 clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. glitch impulse inclu des clock and data feedthrough. 5 ttl input values are 0 v to 3 v, with input rise/fall times of ?3 ns, measured from the 10% an d 90% points. timing reference p oints are 50% for inputs and outputs. 3.3 v dynamic specifications v aa = 3.0 v to 3.6 v 1 , v ref = 1.235 v, r set = 680 , c l = 10 pf. all specifications are t a = 25c, unless otherwise noted, t j max = 110c. table 4. parameter min typ max unit ac linearity spurious-free dynamic range to nyquist 2 single-ended output f clk = 50 mhz; f out = 1.00 mhz 67 dbc f clk = 50 mhz; f out = 2.51 mhz 67 dbc f clk = 50 mhz; f out = 5.04 mhz 63 dbc f clk = 50 mhz; f out = 20.2 mhz 55 dbc f clk = 100 mhz; f out = 2.51 mhz 62 dbc f clk = 100 mhz; f out = 5.04 mhz 60 dbc f clk = 100 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 40.4 mhz 48 dbc f clk = 140 mhz; f out = 2.51 mhz 57 dbc f clk = 140 mhz; f out = 5.04 mhz 58 dbc f clk = 140 mhz; f out = 20.2 mhz 52 dbc f clk = 140 mhz; f out = 40.4 mhz 41 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz 70 dbc f clk = 50 mhz; f out = 2.51 mhz 70 dbc f clk = 50 mhz; f out = 5.04 mhz 65 dbc f clk = 50 mhz; f out = 20.2 mhz 54 dbc f clk = 100 mhz; f out = 2.51 mhz 67 dbc f clk = 100 mhz; f out = 5.04 mhz 63 dbc f clk = 100 mhz; f out = 20.2 mhz 58 dbc f clk = 100 mhz; f out = 40.4 mhz 52 dbc f clk = 140 mhz; f out = 2.51 mhz 62 dbc f clk = 140 mhz; f out = 5.04 mhz 61 dbc f clk = 140 mhz; f out = 20.2 mhz 55 dbc f clk = 140 mhz; f out = 40.4 mhz 53 dbc spurious-free dynamic range within a window single-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 77 dbc f clk = 50 mhz; f out = 5.04 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.04 mhz; 4 mhz span 64 dbc double-ended output f clk = 50 mhz; f out = 1.00 mhz; 1 mhz span 74 dbc f clk = 50 mhz; f out = 5.00 mhz; 2 mhz span 73 dbc f clk = 140 mhz; f out = 5.00 mhz; 4 mhz span 60 dbc
adv7123 rev. d | page 7 of 24 parameter min typ max unit total harmonic distortion f clk = 50 mhz; f out = 1.00 mhz t a = 25c 66 dbc t min to t max 65 dbc f clk = 50 mhz; f out = 2.00 mhz 64 dbc f clk = 100 mhz; f out = 2.00 mhz 64 dbc f clk = 140 mhz; f out = 2.00 mhz 55 dbc dac performance glitch impulse 10 pv-sec dac-to-dac crosstalk 3 23 db data feedthrough 4 , 5 22 db clock feedthrough 4 , 5 33 db 1 these maximum/minimum specifications are guaranteed by characterization over the 3.0 v to 3.6 v range. 2 note that the adv7123 exhibits high performance when operating with an internal voltage reference, v ref . 3 dac-to-dac crosstalk is measured by holding one dac high wh ile the other two are making low-to-high and high-to-low transition s. 4 clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. glitch impulse inclu des clock and data feedthrough. 5 ttl input values are 0 v to 3 v, with input rise/fall times of ?3 ns, measured at the 10% and 90% points. timing reference poi nts are 50% for inputs and outputs. 5 v timing specifications v aa = 5 v 5%, 1 v ref = 1.235 v, r set = 560 , c l = 10 pf. all specifications t min to t max , 2 unless otherwise noted, t j max = 110c. table 5. parameter 3 symbol min typ max unit conditions analog outputs analog output delay t 6 5.5 ns analog output rise/fall time 4 t 7 1.0 ns analog output transition time 5 t 8 15 ns analog output skew 6 t 9 1 2 ns clock control clock frequency 7 f clk 0.5 50 mhz 50 mhz grade 0.5 140 mhz 140 mhz grade 0.5 240 mhz 240 mhz grade data and control setup t 1 0.5 ns data and control hold t 2 1.5 ns clock period t 3 4.17 ns clock pulse width high t 4 1.875 ns f clk_max = 240 mhz clock pulse width low t 5 1.875 ns f clk_max = 240 mhz clock pulse width high t 4 2.85 ns f clk_max = 140 mhz clock pulse width low t 5 2.85 ns f clk_max = 140 mhz clock pulse width high t 4 8.0 ns f clk_max = 50 mhz clock pulse width low t 5 8.0 ns f clk_max = 50 mhz pipeline delay 6 t pd 1.0 1.0 1.0 clock cycles psave up time 6 t 10 2 10 ns 1 these maximum and minimum specificatio ns are guaranteed over this range. 2 temperature range: t min to t max : ?40c to +85 c at 50 mhz and 140 mhz, 0c to 70c at 240 mhz. 3 timing specifications are measured with input levels of 3.0 v (v ih ) and 0 v (v il ) 0 for both 5 v and 3.3 v supplies. 4 rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a fu ll-scale transition. 5 measured from 50% point of full-scale transition to 2% of final value. 6 guaranteed by characterization. 7 f clk maximum specification production tested at 125 mhz; 5 v l imits specified here are guaranteed by characterization.
adv7123 rev. d | page 8 of 24 3.3 v timing specifications v aa = 3.0 v to 3.6 v, 1 v ref = 1.235 v, r set = 560 , c l = 10 pf. all specifications t min to t max , 2 unless otherwise noted, t j max = 110c. table 6. parameter 3 symbol min typ max unit conditions analog outputs analog output delay t 6 7.5 ns analog output rise/fall time 4 t 7 1.0 ns analog output transition time 5 t 8 15 ns analog output skew 6 t 9 1 2 ns clock control clock frequency 7 f clk 50 mhz 50 mhz grade 140 mhz 140 mhz grade 240 mhz 240 mhz grade 330 mhz 330 mhz grade data and control setup t 1 0.2 ns data and control hold t 2 1.5 ns clock period t 3 3 ns clock pulse width high 6 t 4 1.4 ns f clk_max = 330 mhz clock pulse width low 6 t 5 1.4 ns f clk_max = 330 mhz clock pulse width high t 4 1.875 ns f clk_max = 240 mhz clock pulse width low t 5 1.875 ns f clk_max = 240 mhz clock pulse width high t 4 2.85 ns f clk_max = 140 mhz clock pulse width low t 5 2.85 ns f clk_max = 140 mhz clock pulse width high t 4 8.0 ns f clk_max = 50 mhz clock pulse width low t 5 8.0 ns f clk_max = 50 mhz pipeline delay 6 t pd 1.0 1.0 1.0 clock cycles psave up time 6 t 10 4 10 ns 1 these maximum and minimum specificatio ns are guaranteed over this range. 2 temperature range: t min to t max : ?40c to +85c at 50 mh z and 140 mhz, 0c to 70 c at 240 mhz and 330 mhz. 3 timing specifications are measured with input levels of 3.0 v (v ih ) and 0 v (v il ) 0 for both 5 v and 3.3 v supplies. 4 rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a fu ll-scale transition. 5 measured from 50% point of full-scale transition to 2% of final value. 6 guaranteed by characterization. 7 f clk maximum specification production tested at 125 mhz; 5 v l imits specified here are guaranteed by characterization. t 3 t 1 t 4 t 8 t 2 t 6 t 7 t 5 clock digital inputs (r9 to r0, g9 to g0, b9 to b0, sync, blank) analog outputs (ior, ior, iog, iog, iob, iob) notes 1. output delay ( t 6 ) measured from the 50% point of the rising edge of clock to the 50% point of full-scale transition. 2. output rise/fall time ( t 7 ) measured between the 10% and 90% points of full-scale transition. 3. transition time ( t 8 ) measured from the 50% point of full-scale transition to within 2% of the final output value. 00215-002 figure 2. timing diagram
adv7123 rev. d | page 9 of 24 absolute maximum ratings table 7. parameter rating v aa to gnd 7 v voltage on any digital pin gnd ? 0.5 v to v aa + 0.5 v ambient operating temperature (t a ) ?40c to +85c storage temperature (t s ) ?65c to +150c junction temperature (t j ) 150c lead temperature (soldering, 10 sec) 300c vapor phase soldering (1 minute) 220c i out to gnd 1 0 v to v aa 1 analog output short circuit to any po wer supply or common gnd can be of an indefinite duration. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adv7123 rev. d | page 10 of 24 pin configuration and fu nction descriptions v aa b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 clock r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 psave r set g0 g1 g2 g3 g4 g5 g6 g7 g8 g9 comp v aa v aa iob gnd gnd v ref iob iog iog ior ior blank sync 00215-003 48 47 46 45 44 43 42 41 40 39 38 37 35 34 33 30 31 32 36 29 28 27 25 26 2 3 4 7 6 5 1 8 9 10 12 11 13 14 15 16 17 18 19 20 21 22 23 24 pin 1 indicator adv7123 top view (not to scale) figure 3. pin configuration table 8. pin function descriptions pin no. mnemonic description 1 to 10, 14 to 23, 39 to 48 g0 to g9, b0 to b9, r0 to r9 red, green, and blue pixel data inputs (ttl compatible). pixel data is latched on the rising edge of clock. r0, g0, and b0 are the least significant data bits. unused pixel data inputs should be connected to either the regular printed circuit board (pcb) power or ground plane. 11 blank composite blank control input (ttl compatible). a logi c 0 on this control input drives the analog outputs, ior, iob, and iog, to the blanking level. the blank signal is latched on the rising edge of clock. while blank is a logic 0, the r0 to r9, g0 to g9, and b0 to b9 pixel inputs are ignored. 12 sync composite sync control input (ttl compatible). a logic 0 on the sync input switches off a 40 ire current source. this is internally conn ected to the iog analog output. sync does not override any other control or data input; therefore, it should only be asserted during the blanking interval. sync is latched on the rising edge of clock. if sync information is not required on the green channel, the sync input should be tied to logic 0. 13, 29, 30 v aa analog power supply (5 v 5%). all v aa pins on the adv7123 must be connected. 24 clock clock input (ttl compatible). the rising edge of clock latches the r0 to r9, g0 to g9, b0 to b9, sync , and blank pixel and control inputs. it is typically the pixel clock rate of the video system. clock should be driven by a dedicated ttl buffer. 25, 26 gnd ground. all gnd pins must be connected. 27, 31, 33 iob , iog , ior differential red, green, and blue current output s (high impedance current sources). these rgb video outputs are specified to directly drive rs-343a and rs- 170 video levels into a doubly terminated 75 load. if the complementary outputs are not required, these outputs should be tied to ground. 28, 32, 34 iob, iog, ior red, green, and blue current outputs. these high impedan ce current sources are capable of directly driving a doubly terminated 75 coaxial cable. all three curren t outputs should have simil ar output loads whether or not they are all being used. 35 comp compensation pin. this is a compensation pin for the in ternal reference amplifier. a 0.1 f ceramic capacitor must be connected between comp and v aa . 36 v ref voltage reference input for dacs or voltage reference output (1.235 v).
adv7123 rev. d | page 11 of 24 pin no. mnemonic description 37 r set a resistor (r set ) connected between this pin and gnd controls the magnitude of the full-scale video signal. note that the ire relationships are maintained, regardless of the full-sc ale output current. for nominal video levels into a doubly terminated 75 load, r set = 530 . the relationship between r set and the full-scale output current on iog (assuming i sync is connected to iog) is given by: r set () = 11,445 v ref (v)/ iog (ma) the relationship between r set and the full-scale output current on ior, iog, and iob is given by: iog (ma) = 11,445 v ref (v)/ r set () ( sync being asserted) ior, iob (ma) = 7989.6 v ref (v)/ r set () the equation for iog is the same as that for ior and iob when sync is not being used, that is, sync tied permanently low. 38 psave power save control pin. reduced power consumption is available on the adv7123 when this pin is active.
adv7123 rev. d | page 12 of 24 typical performance characteristics 5 v typical performance characteristics v aa = 5 v, v ref = 1.235 v, i out = 17.62 ma, 50 doubly terminated load, differential output loading, t a = 25c, unless otherwise noted. f clk (mhz) 74 58 thd (dbc) 50 100 140 72 70 68 64 60 66 76 62 0 160 fourth harmonic third harmonic second harmonic 00215-007 f out (mhz) 70 0 0.1 1 sfdr (dbc) 20.2 2.51 40.4 60 50 40 20 10 30 sfdr (de) sfdr (se) 100 5.04 00215-004 figure 4. sfdr vs. f out @ f clk = 140 mhz (single-ended and differential) figure 7. thd vs. f clk @ f out = 2 mhz (second, third, and fourth harmonics) i out (ma) 0.9 0 linearity (lsb) 0.8 0.7 0.6 0.4 0.2 0.5 1.0 0.3 17.62 2 0.1 00215-008 70 0 sfdr (dbc) 60 50 40 20 10 30 80 sfdr (se) sfdr (de) f out (mhz) 0.1 1 20.2 2.51 40.4 100 5.04 00215-005 figure 5. sfdr vs. f out @ f clk = 50 mhz (single-en ded and differential) figure 8. linearity vs. i out temperature (c) 71.8 70.4 sfdr (dbc) 71.6 71.4 71.2 70.8 70.6 71.0 72.0 85 65 45 ?10 25 5 0 0215-006 code (inl) ?1.0 error (lsb) 0.5 ?0.5 0 1.0 0.75 1023 ?0.16 00215-009 figure 6. sfdr vs. temperature @ f clk = 50 mhz (f out = 1 mhz) figure 9. typical linearity (inl)
adv7123 rev. d | page 13 of 24 ?85 sfdr (dbm) ?45 ? 5 0khz start 35mhz 70mhz stop 00215-010 figure 10. single-tone sfdr @ f clk = 140 mhz (f out = 2 mhz) ?85 sfdr (dbm) ?45 ? 5 0khz start 35mhz 70mhz stop 00215-011 figure 11. single-tone sfdr @ f clk = 140 mhz (f out = 20 mhz) 0khz start ?85 sfdr (dbm) ?45 ? 5 35mhz 70mhz stop 00215-012 figure 12. dual-tone sfdr @ f clk = 140 mhz (f out1 = 13.5 mhz, f out2 = 14.5 mhz)
adv7123 rev. d | page 14 of 24 3 v typical performance characteristics v aa = 3 v, v ref = 1.235 v, i out = 17.62 ma, 50 doubly terminated load, differential output loading, t a = 25c. 70 0 sfdr (dbc) 60 50 40 20 10 30 sfdr (se) sfdr (de) f out (mhz) 1.0 20.2 2.51 40.4 100 5.04 00215-013 figure 13. sfdr vs. f out @ f clk = 140 mhz (single-en ded and differential) 70 0 sfdr (dbc) 60 50 40 20 10 30 80 sfdr (se) sfdr (de) f out (mhz) 0.1 1 20.2 2.51 40.4 100 5.04 00215-014 figure 14. sfdr vs. f out @ f clk = 140 mhz (single-en ded and differential) temperature (c) 71.8 70.4 sfdr (dbc) 20 85 145 71.6 71.4 71.2 70.8 70.6 71.0 72.0 165 0 0 0215-015 figure 15. sfdr vs. temperature @ f clk = 50 mhz, (f out = 1 mhz) frequency (mhz) 74 58 thd (dbc) 72 70 68 64 60 66 76 62 50 100 140 0 160 second harmonic third harmonic fourth harmonic 0 0215-016 figure 16. thd vs. f clk @ f out = 2 mhz (second, third, and fourth harmonics) 0.9 0 linearity (lsb) 2 0.8 0.7 0.6 0.4 0.2 0.5 1.0 0.3 17.62 0.1 i out (ma) 00215-017 figure 17. linearity vs. i out code (inl) ?1.0 linearity (lsb) 0.5 ?0.5 0 1.0 0.75 1023 ?0.42 00215-018 figure 18. typical linearity
adv7123 rev. d | page 15 of 24 ?85 sfdr (dbm) ?45 ? 5 0khz start 35mhz 70mhz stop 00215-019 figure 19. single-tone sfdr @ f clk = 140 mhz (f out = 2 mhz) ?85 sfdr (dbm) ?45 ? 5 0khz start 35mhz 70mhz stop 00215-020 figure 20. single-tone sfdr @ f clk = 140 mhz (f out = 20 mhz) ?85 sfdr (dbm) ?45 ? 5 0khz start 35mhz 70mhz stop 00215-021 figure 21. dual-tone sfdr @ f clk = 140 mhz (f out1 = 13.5 mhz, f out2 = 14.5 mhz)
adv7123 rev. d | page 16 of 24 terminology blanking level the level separating the sync portion from the video portion of the waveform. usually referred to as the front porch or back porch. at 0 ire units, it is the level that shuts off the picture tube, resulting in the blackest possible picture. color video (rgb) this refers to the technique of combining the three primary colors of red, green, and blue to produce color pictures within the usual spectrum. in rgb monitors, three dacs are required, one for each color. sync signal ( sync ) the position of the composite video signal that synchronizes the scanning process. gray scale the discrete levels of video signal between reference black and reference white levels. a 10-bit dac contains 1024 different levels, while an 8-bit dac contains 256. raster scan the most basic method of sweeping a crt one line at a time to generate and display images. reference black level the maximum negative polarity amplitude of the video signal. reference white level the maximum positive polarity amplitude of the video signal. sync level the peak level of the sync signal. video signal the portion of the composite video signal that varies in gray scale levels between reference white and reference black. also referred to as the picture signal, this is the portion that can be visually observed.
adv7123 rev. d | page 17 of 24 circuit description and operation the adv7123 contains three 10-bit dacs, with three input channels, each containing a 10-bit register. also integrated on board the part is a reference amplifier. the crt control functions, blank and sync , are integrated on board the adv7123. digital inputs there are 30 bits of pixel data (color information), r0 to r9, g0 to g9, and b0 to b9, latched into the device on the rising edge of each clock cycle. this data is presented to the three 10-bit dacs and then converted to three analog (rgb) output waveforms (see figure 22 ). clock data digital inputs (r9 to r0, g9 to g0, b9 to b0, sync, blank) analog outputs (ior, ior, iog, iog, iob, iob) 00215-022 figure 22. video data input/output the adv7123 has two additional control signals that are latched to the analog video outputs in a similar fashion. blank and sync are each latched on the rising edge of clock to maintain synchronization with the pixel data stream. the blank and sync functions allow for the encoding of these video synchronization signals onto the rgb video output. this is done by adding appropriately weighted current sources to the analog outputs, as determined by the logic levels on the blank and sync digital inputs. shows the analog output, rgb video waveform of the adv7123. the influence of figure 23 sync and blank on the analog video waveform is illustrated. table 9 details the resultant effect on the analog outputs of blank and sync . all these digital inputs are specified to accept ttl logic levels. clock input the clock input of the adv7123 is typically the pixel clock rate of the system. it is also known as the dot rate. the dot rate, and thus the required clock frequency, is determined by the on-screen resolution, according to the following equation: dot rate = ( horiz res ) (vert res) (refresh rate )/ ( retrace factor ) where: horiz res is the number of pixels per line. ver t res is the number of lines per frame. refresh rate is the horizontal scan rate. this is the rate at which the screen must be refreshed, typically 60 hz for a noninterlaced system, or 30 hz for an interlaced system. retrace factor is the total blank time factor. this takes into account that the display is blanked for a certain fraction of the total duration of each frame (for example, 0.8). therefore, for a graphics system with a 1024 1024 resolution, a noninterlaced 60 hz refresh rate, and a retrace factor of 0.8, dot rate = 1024 1024 60/0.8 = 78.6 mhz the required clock frequency is thus 78.6 mhz. all video data and control inputs are latched into the adv7123 on the rising edge of clock, as described in the digital inputs section. it is recommended that the clock input to the adv7123 be driven by a ttl buffer (for example, 74f244). red and blue notes 1. outputs connected to a doubly terminated 75 ? load. 2. v ref = 1.235v, r set = 530 ? . 3. rs-343 levels and tolerances assumed on all levels. ma v 18.67 0.7 00 ma v 26.0 0.975 white level blank level sync level 7.2 0.271 00 green 00215-023 figure 23. typical rgb vi deo output waveform
adv7123 rev. d | page 18 of 24 table 9. typical video output truth table (r set = 530 , r load = 37.5 ) video output level iog (ma) iog (ma) ior/iob (ma) ior / iob (ma) sync blank dac input data white level 26.0 0 18.67 0 1 1 0x3ffh video video + 7.2 18.67 ? video video 18.67 ? video 1 1 data video to blank video 18.67 ? video video 18.67 ? video 0 1 data black level 7.2 18.67 0 18.67 1 1 0x000h black to blank 0 18.67 0 18.67 0 1 0x000h blank level 7.2 18.67 0 18.67 1 0 0xxxxh (dont care) sync level 0 18.67 0 18.67 0 0 0xxxxh (dont care) video synchronization and control the adv7123 has a single composite sync ( sync ) input control. many graphics processors and crt controllers have the ability of generating horizontal sync (hsync), vertical sync (vsync), and composite sync . in a graphics system that does not automatically generate a composite sync signal, the inclusion of some additional logic circuitry enables the generation of a composite sync signal. the sync current is internally connected directly to the iog output, thus encoding video synchronization information onto the green video channel. if it is not required to encode sync information onto the adv7123, the sync input should be tied to logic low. reference input the adv7123 contains an on-board voltage reference. the v ref pin is normally terminated to v aa through a 0.1 f capacitor. alternatively, the part can, if required, be overdriven by an external 1.23 v reference (ad1580). a resistance, r set , connected between the r set pin and gnd, determines the amplitude of the output video level according to equation 1 and equation 2 for the adv7123. iog (ma) = 11,445 v ref (v)/ r set () (1) ior , iob (ma) = 7989.6 v ref (v)/ r set () (2) equation 1 applies to the adv7123 only, when sync is being used. if sync is not being encoded onto the green channel, equation 1 is similar to equation 2. using a variable value of r set allows for accurate adjustment of the analog output video levels. use of a fixed 560 r set resistor yields the analog output levels quoted in the specifications section. these values typically correspond to the rs-343a video wave- form values, as shown in figure 23 . dacs the adv7123 contains three matched 10-bit dacs. the dacs are designed using an advanced, high speed, segmented architec- ture. the bit currents corresponding to each digital input are routed to either the analog output (bit = 1) or gnd (bit = 0) by a sophisticated decoding scheme. because all this circuitry is on one monolithic device, matching between the three dacs is optimized. as well as matching, the use of identical current sources in a monolithic design guarantees monotonicity and low glitch. the on-board operational amplifier stabilizes the full-scale output current against temperature and power supply variations. analog outputs the adv7123 has three analog outputs, corresponding to the red, green, and blue video signals. the red, green, and blue analog outputs of the adv7123 are high impedance current sources. each one of these three rgb current outputs is capable of directly driving a 37.5 load, such as a doubly terminated 75 coaxial cable. figure 24 shows the required configuration for each of the three rgb outputs connected into a doubly terminated 75 load. this arrangement develops rs-343a video output voltage levels across a 75 monitor. a suggested method of driving rs-170 video levels into a 75 monitor is shown in figure 25 . the output current levels of the dacs remain unchanged, but the source termination resistance, z s , on each of the three dacs is increased from 75 to 150 . ior, iog, iob z s = 75 ? (source termination) termination repeated three times for red, green, and blue dacs z l = 75 ? (monitor) z 0 = 75 ? (cable) dacs 00215-024 figure 24. analog output termination for rs-343a ior, iog, iob z s = 150 ? (source termination) termination repeated three times for red, green, and blue dacs z l = 75 ? (monitor) z 0 = 75 ? (cable) dacs 00215-025 figure 25. analog output termination for rs-170 more detailed information regarding load terminations for various output configurations, including rs-343a and rs-170, is available in the an-205 application note, video formats and required load terminations, available from analog devices, at www.analog.com .
adv7123 rev. d | page 19 of 24 figure 23 shows the video waveforms associated with the three rgb outputs driving the doubly terminated 75 load of figure 24 . as well as the gray scale levels, black level to white level, figure 23 also shows the contributions of sync and blank for the adv7123. these control inputs add appropriately weighted currents to the analog outputs, producing the specific output level requirements for video applications. details how the tabl e 9 sync and blank inputs modify the output levels. gray scale operation the adv7123 can be used for standalone, gray scale (mono- chrome), or composite video applications (that is, only one channel used for video information). any one of the three channels, red, green, or blue, can be used to input the digital video data. the two unused video data channels should be tied to logic 0. the unused analog outputs should be terminated with the same load as that for the used channel; that is, if the red channel is used and ior is terminated with a doubly terminated 75 load (37.5 ), iob and iog should be terminated with 37.5 resistors (see figure 26 ). r0 r9 g0 adv7123 g9 b0 b9 ior iog 37.5 ? doubly terminated 7.5 ? load video output 37.5 ? iob gnd 0 0215-026 figure 26. input and output connections for standalone gray scale or composite video video output buffers the adv7123 is specified to drive transmission line loads. the analog output configuration to drive such loads is described in the analog outputs section and illustrated in figure 27 . however, in some applications it may be required to drive long transmis- sion line cable lengths. cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. the inclusion of output buffers compensates for some cable distortion. buffers with large full power bandwidths and gains between two and four are required. these buffers also need to be able to supply sufficient current over the complete output voltage swing. analog devices produces a range of suitable op amps for such applications. these include the ad843, ad844, ad847 , and ad848 series of monolithic op amps. in very high frequency applications (80 mhz), the ad8061 is recommended. more information on line driver buffering circuits is given in the relevant op amp data sheets. use of buffer amplifiers also allows implementation of other video standards besides rs-343a and rs-170. altering the gain components of the buffer circuit results in any desired video level. 3 6 2 z l = 75 ? (monitor) z 0 = 75 ? z 2 z 1 +v s ?v s 0.1f 0.1f 75 ? (cable) gain (g) = 1 + dacs ior, iog, iob z s = 75 ? (source termination) ad848 7 4 z 1 z 2 00215-027 figure 27. ad848 as an output buffer pcb layout considerations the adv7123 is optimally designed for lowest noise perfor- mance, both radiated and conducted noise. to complement the excellent noise performance of the adv7123, it is imperative that great care be given to the pcb layout. figure 28 shows a recommended connection diagram for the adv7123. the layout should be optimized for lowest noise on the adv7123 power and ground lines. this can be achieved by shielding the digital inputs and providing good decoupling. shorten the lead length between groups of v aa and gnd pins to minimize inductive ringing. it is recommended to use a 4-layer printed circuit board with a single ground plane. the ground and power planes should separate the signal trace layer and the solder side layer. noise on the analog power plane can be further reduced by using multiple decoupling capacitors (see figure 28 ). optimum performance is achieved by using 0.1 f and 0.01 f ceramic capacitors. individually decouple each v aa pin to ground by placing the capacitors as close as possible to the device with the capacitor leads as short as possible, thus minimizing lead inductance. it is important to note that while the adv7123 contains circuitry to reject power supply noise, this rejection decreases with frequency. if a high frequency switching power supply is used, pay close attention to reducing power supply noise. a dc power supply filter (murata bnx002) provides emi suppression between the switching power supply and the main pcb. alternatively, consideration can be given to using a 3- terminal voltage regulator. digital signal interconnect isolate the digital signal lines to the adv7123 as much as possible from the analog outputs and other analog circuitry. digital signal lines should not overlay the analog power plane. due to the high clock rates used, long clock lines to the adv7123 should be avoided to minimize noise pickup. connect any active pull-up termination resistors for the digital inputs to the regular pcb power plane (v cc ) and not the analog power plane.
adv7123 rev. d | page 20 of 24 analog signal interconnect for optimum performance, the analog outputs should each have a source termination resistance to ground of 75 (doubly terminated 75 configuration). this termination resistance should be as close as possible to the adv7123 to minimize reflections. place the adv7123 as close as possible to the output connec- tors, thus minimizing noise pickup and reflections due to impedance mismatch. the video output signals should overlay the ground plane and not the analog power plane, thereby maximizing the high frequency power supply rejection. additional information on pcb design is available in the an-333 application note, design and layout of a video graphics system for reduced emi, which is available from analog devices at www.analog.com . 35 36 37 33 31 27 r9 to r0 39 to 48 comp v aa v aa v aa v aa v ref r set ior 75? 75? 75? coaxial cable 75? power supply decouplin g (0.1f and 0.01f capacitor for each v aa group) ad1580 adv7123 monitor (crt) 1 2 bnc connectors complementary outputs 75? 1k? r set 530 ? iog iob 12 sync 11 blank 24 clock 38 psave gnd 25, 26 13, 29, 30 video data inputs g9 to g0 1to 10 b9 to b0 14 to 23 ior iog iob 75? 75? 32 28 34 0.1f 0.1f 1f 0.01f 00215-028 figure 28. typical connection diagram
adv7123 rev. d | page 21 of 24 outline dimensions compliant to jedec standards ms-026-bbc top view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706-a figure 29. 48-lead low profile quad flat package [lqfp] (st-48) dimensions shown in millimeters ordering guide model 1 , 2 temperature range speed option pa ckage description package option adv7123kstz50 ?40c to +85c 50 mhz 48-lead lqfp st-48 ADV7123KSTZ140 ?40c to +85c 140 mhz 48-lead lqfp st-48 adv7123kst140-rl ?40c to +85c 140 mhz 48-lead lqfp st-48 adv7123jstz240 0c to 70c 240 mhz 48-lead lqfp st-48 adv7123jstz240-rl 0c to 70c 240 mhz 48-lead lqfp st-48 adv7123jstz330 0c to 70c 330 mhz 48-lead lqfp st-48 1 z = rohs compliant part. 2 adv7123jstz330 is available in a 3.3 v version only.
adv7123 rev. d | page 22 of 24 notes
adv7123 rev. d | page 23 of 24 notes
adv7123 rev. d | page 24 of 24 notes ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00215-0-7/10(d)

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